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MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC DESCRIPTION
The M64897GP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR/PC using I 2C BUS control. It contains the prescaler with operating up to1.3GHz, 4 band drivers and DC-DC converter for Tuning voltage.
PRESCALER INPUT GND SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 BAND SWITCHING OUTPUTS fin GND VCC1 VCC2 BS4 BS3 BS2 1 2 3 4 5 6 7 8 9 10 20 Xin 19 ADS 18 SDA 17 SCL CRYSTAL OSCILLATOR CHIP ADDRESS INPUT DATA INPUT CLOCK INPUT
PIN CONFIGURATION (TOP VIEW)
M64897GP
FEATURES
* * * * * * * *
Built-in DC-DC converter for Tuning voltage 4 integrated PNP band drivers (Io=30mA, Vsat=0.2V typ@Vcc1 to 10V) Built-in prescaler with input amplifier (f max=1.3GHz) PLL lock/unlock status display out put (Built-in pull up resistor) X'tal 4MHz is used to realize 3 type of tuning steps (Divider ratio 1/512, 1/640, 1/1024) Software compatible with M64894 Built-in Power on reset system Small Package (SSOP)
16 LD/ftest LD/ftest OUTPUT A/D INPUT 15 ADC 14 Vin 13 Vtu 12 11 +B SWE FILTER INPUT TUNING OUTPUT SUPPLY VOLTAGE SWITCHING OUTPUT
BS1 DC-DCSUPPLY VDC VOLTAGE PEACK CURRENT Ipk DETECT
Outline 20P2E-A
RECOMMENDED OPERATING CONDITION APPLICATION
PC, TV, VCR tuners Supply voltage range..............................................V CC1=4.5 to 5.5V VCC2=VCC1 to 10V Rated supply voltage...........................................................V CC1=5V VCC2=VCC1
BLOCK DIAGRAM
VCC1 3 VDC 9 SQ Xin 20 OSC f REF DIVIDER SELECTER DIV. R 11 SWE LATCH fin 1 AMP 1/8 LATCH 15 2 Ipk 10
+
PHASE DETECTOR CHARGE PUMP CP 1 LOCK DETECTOR 5 TEST LATCH 14 Vin Vreg 12 +B 15bit PROGRAMMABLE DIVIDER 13 Vtu OS
1/32,1/33
SCL 17 BUS CONTROLLER ADDRESS SELECT
SDA 18
ADS 19 4 BAIS / BAND SWITCH DRIVER 1 Power On Reset 4 VCC2 5 BS4 6 BS3 7 BS2 8 BS1 2 GND
3
5-LEVEL A/D
16 LD/ftest
15 ADC
1
MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC DESCRIPTION OF PIN
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol f in GND VCC1 VCC2 BS4 BS3 BS2 BS1 VDC Ipk SWE +B Vtu DC-DC power supply voltage Peack current detect Switching output Power supply voltage Tuning output Band switching outputs GND
Power supply voltage 1 Power supply voltage 2
Pin name Prescaler input Input for the VCO frequency. Ground to 0V.
Function
Power supply voltage terminal. 5.0V0.5V Power supply for band switching, Vcc1 to 10V PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF. DC-DC power supply voltage terminal. 5.0V 0.5V When potential difference with VDC terminal becomes more than 0.33V by current limiting detector of DC-DC converter, the listing rises with off. DC-DC converter oscillator output. Power supply voltage for turning voltage. This supplies the tuning voltage. This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference
14
Vin
Filter input
(Charge pump output)
frequency (fREF), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. Lock detector output. When loop of phase locked loop locked it, it rises with "H" level in "L" level or unlock. In control byte data input, the programmabule freq. divider output and reference freq. output is selected by the test mode. A/D conversion of the input voltage. Data is read into the shift register when the clock signal falls. Input for band SW and programmable freq. divider set up. In lead mode, itoutputs lock detector output and power down flag and a state of 5 level A/D converter. Chip address sets it up with the input condition of terminal. 4.0MHz crystal oscillator is connected.
15
LD/ftest
Lock detect /Test port
16 17 18 19 20
ADC SCL SDA ADS X in
AD converter input Clock input Data input
Address switching input
This is connected to the crystal oscillator
ABSOLUTE MAXIMUM RATINGS (Ta=-20C to +75C, unless otherwise noted)
Symbol VCC1 VCC2 VI VO VBSOFF IBSON tBSON Pd Topr Tstg Parameter Supply voltage 1 Supply voltage 2 Input voltage Output voltage Voltage applied when the band output is OFF Band output current ON the time when the band output is ON Power dissipation Operating temperature Storage temperature per 1 band output circuit 40mA per 1 band output circuit 3circuits are pn at same time, Ta=75C Conditions Pin3 Pin4 Not to exceed Vcc1 fREF output Ratings 6.0 10.8 6.0 6.0 10.8 40.0 10 255 -20 to +75 -40 to +125 Unit V V V V V mA sec mW C C
2
MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC RECOMMENDED OPERATING CONDITIONS (Ta=-20C to +75C, unless otherwise noted)
Symbol VCC1 VCC2 fopr1 fopr2 IBDL Parameter Supply voltage 1 Supply voltage 2 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Conditions Pin3 Pin4 Crystal oscillation circuit Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. Ratings 4.5 to 5.5 VCC1 to 10.0 4.0 80 to 1300 0 to 30 Unit V V V MHz mA
ELECTRICAL CHARACTERISTICS (Ta=-20C to +75C, unless otherwise noted, Vcc1=5.0V, Vcc2=9.0V)
Symbol VIH VIL IIH IIL VOL ILO VOH VOL VBS Iolk1 VtoH VtoL Icpo IcpLK ICC1 ICC2A ICC2B Parameter "H" input voltage Input terminals SDA output Lock output Band SW Tuning output Charge pump "L" input voltage "H" input current "L" input current "L" output voltage Leak current "H" output voltage "L" output voltage output voltage Leak current output voltage "H" output voltage "L" "H" output current Test pin 17 to 18 17 to 18 17 to 18 17/18 18 18 16 16 5 to 8 5 to 8 13 13 14 14 3 4 4 4 9 12 11 10 VCC1=5.5V, Vi=4.0V VCC1=5.5V, Vi=0.4V VCC1=5.5V, Ic=3mA VCC1=5.5V, Vo=5.5V VCC1=5.5V VCC1=5.5V VCC2=9V, Io=-30mA VCC2=9V, Band SW is OFF Vo=0V +B=31V +B=31V VCC1=5.0V, Vo=2.5V VCC1=5.0V, Vo=2.5V VCC1=5.5V VCC2=9V VCC2=9V VCC2=9V, Io=-30mA VCC1=5.5V VCC1=5.5V VCC1=5.5V VCC1=5.5V Test conditions Min. 3.0 - - - - - 5.0 11.6 - 30.5 - - - - - - - - 28 - - Limits Typ. Max. VCC1+0.3 - - - -4/-14 - - - 0.3 11.8 - - 0.2 270 - 20 - 4.0 34.0 1.3 31 571 330 1.5 10 -10/-30 0.4 10 - 0.5 - -10 - 0.4 370 50 30 0.3 6.0 36.0 3.0 35 - - Unit V V A A A A V V V A V V A nA mA mA mA mA mA V kHz mV
Leak current Supply current 1 Supply current 2 4 circuits OFF 1 circuits ON, Output open Output current 30mA
ICC2C DC-DC Converter ICCdc Supply current (action) Vdo Output voltage fOSC OSC frequency Current limit detect voltage Vipk
The typical values are at VCC1=5.0V, VCC2=9.0V, Ta=+25C.
3
MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC SWITCHING CHARACTERISTICS (Ta=-20C to +75C, unless otherwise noted, Vcc1=5.0V, Vcc2=9.0V)
Symbol fopr Parameter Prescaler operating frequency Test pin 1 Test conditions VCC1=4.5 to 5.5V Vin=Vinmin to Vinmax 850 to 100MHz VCC1=4.5 100 to 950MHz to 5.5V 950 to 1300MHz VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V Min. 80 -24 -27 -15 0 4.7 4 4.7 4 4.7 0 250 - - 4 Limits Typ. - - - - - - - - - - - - - - - Max. 1300 4 4 4 100 - - - - - - - 1000 300 - Unit MHz
Vin fSCL tBUF tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tR tF tSUSTO
Operation input voltage Clock pulse frequency Bus free time Data hold time SCL low hold time SCL high hold time Set up time Data hold time Data set up time Rise time Fall time Set up time
1 17 18 17 17 17 17, 18 17, 18 17, 18 17, 18 17, 18 17, 18
dBm kHz s s s s s s ns ns ns s
4
MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC METHOD OF SETTING DATA
The input information to consit of 2 or data of 4bytes to lead to Chip Address is received in I C bus receiver. It shows a definition of bus protocol admitted in the following. 1_STA 2_STA 3_STA 4_STA CA CA CA CA CB D1 CB D1 BB D2 BB D2 STO STO D1 CB D2 BB STO STO
2
The information of 5 bytes necessary for circuit operation is chip address and control data, bandS.W. data of 2 bytes and divider byte of 2 bytes. After the chip address input, 2 or data of 4 bytes are received. Function bit is contained the first and the third data byte to distinguish between divider data and control data, band data, and "0" goes ahead of divider data, and "1" goes ahead of control data, bandS.W. data.
STA : Start condition STO : Stop condition CA CB BB D1 D2 : Chip address : Control data byte : BandS.W. data byte : Divider data byte : Divider data byte
SDA
SCL S STA
1-7 ADDRESS CA
8 R/W
9 ACK
1-7 DATA
8
9 ACK
1-7 DATA
8
9 ACK P STO
Write mode format Byte Address Byte Devider Byte1 Devider Byte2 Control Byte1 Band SW Byte Read mode format Byte Address Byte Status Byte1 MSB 1 POR LSB A A MSB 1 0 N7 1 X LSB A A A A A
1 N14 N6 X X
0 N13 N5 T2 X
0 N12 N4 T1 X
0 N11 N3 T0 BS4
MA1 N10 N2 Rsa BS3
MA0 N9 N1 Rsb BS2
0 N8 N0 OS BS1
1 FL
0 X
0 X
0 X
MA1 A2
MA0 A1
1 A0
5
MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC
DATA CORDING EXAMPLE
Write mode format example Byte Address Byte Devider Byte1 Devider Byte2 Control Byte1 Band SW Byte MSB 1 0 1 1 0 LSB 1 1 1 1 1 Condition in data setting ADS input VCC1 Divider ratio N=16544 fREF divider ratio 1/1024 BS4 output ON
1 1 0 1 0
0 0 1 0 0
0 0 0 0 0
0 0 0 0 1
1 0 0 0 0
1 0 0 1 0
0 0 0 0 0
fVCO=Nx8xfREF =16544x8x(4MHz/1024)=517MHz Read mode format example (Loop locked) Byte Address Byte Status Byte MSB 1 0 1 1 0 1 0 1 0 1 1 0 1 1 1 1 LSB 1 1 Condition in device ADS Applied voltage 0.9VCC1 to VCC1 ADS Applied voltage 0.45VCC1 to 0.6VCC1
Use data input for "1" so that the data of Read mode and Write mode return ACK signal "0" to micro computer in 9bits of each byte.
TEST MODE DATA SET UP METHOD
Test Mode Bit Set Up X : Random, 0 or 1. normal "0" T2, T1, T0 : Setting up for the test mode T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge pump
Normal operation
MA1 ,MA0 : Programmabule Address Bit Address input voltage 0 to 0.1VCC1 Always valid 0.4VCC1 to 0.6VCC1 0.9VCC1 to VCC1 MA1 0 0 1 1 MA0 0 1 0 1
High impedance Sink Source High impedance High impedance
12 pin condition ADC input ADC input ADC input ADC input fREF output f1/N output
Mode
Normal operation
Test mode Test mode Test mode Test mode Test mode
N14 to N0 : How to set dividing ratio of the programable the divider RSa, RSb : Set up for the reference Frequency divider ratio Divider ratio=N14(214=16384)+ +N0(20=1) Therefore, the range of divider N is 1,024 to 32,768 Example) fvco=fREFx8xN =3.90625x8xN =31.25xN (kHz) OS : Set up the tuning amplifier OS 0 1 Tuning voltage output ON OFF Mode Normal Test RSa 1 0 X RSb 1 1 0 Divider ratio 1/512 1/1024 1/640
POR : Power on reset flag. "1" output at reset FL : Lock detector flag. "1" output at locked, "0" output at unlocked
6
MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC Power on reset operation (Initial state the power is turned ON)
BS4 to BS1 Charge pump Tuning amplifier Charge pump current Frequency divider ratio Lock detect : OFF : High impedance : OFF : 270A : 1/1024 :H
A2, A1, A0 : 5level A/D converter output data ADC input voltage 0.6VCC1 to VCC1 0.45VCC1 to 0.6VCC1 0.3VCC1 to 0.45VCC1 0.15VCC1 to 0.3VCC1 0 to 0.15VCC1 A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0
The voltage accuracy allowance range : 0.03VCC1 [V]
Charge pump current is replaced by 70A when locks it by automatic change facility.
TIMING DIAGRAM
START condition
SDA tBUF tLOW tR tF tHDSTA
SCL
tHDSTA STOP condition
tHDDAT
tHIGH
tSUDAT
tSUSTA START condition
tSUSTO STOP condition
CRYSTAL OSCILLATOR CONNECTION DIAGRAM
16
Crystal oscillator characteristics Actual resistance : less then 300 Load capacitance : 20pF 18pF
4MHz
7
MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC APPLICATION EXAMPLE
BUILT-IN PLL TUNER IF AGC
IF
AGC
VHF 4-BAND TUNER UHF
AFT
Note) Filter constant is for reference. Add a capacitor to stabilize the filter circuit.
+B
BS4
BS3
BS2
BS1
LO
VT
-
0.01F 1000pF 1500pF 56k 100pF 56k 0.1F
33H 0.1F 43
VCC1 to 9V
22k 13 9
68H 10 11
M64897GP
4
5
6
7
8
1
14
AMP BIAS CIRCUIT Q S BAND DRIVER 4 1/32 1/33 1/8 CHARGE PUMP +PHASE DETECTOR Vreg 1.5F OSC DIVIDER MAIN COUNTER 10 LOCK DETECTOR 12 2 18pF 20 5LEVEL A/DC 4MHz R
3 +5V
POWER ON RESET
SWALLOW COUNTER
I2 5 CHIP SELECT
C RECIEVER
VCC1 =5V 51k
15
-
1000pF
Vcc1
19
17
18
ADS MCU
SCL
SDA
LD/ftest
Units Resistance : Capacitance : F
8

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